makefile help

[v***@gmail.com]

Hi,
I have small project which has several subdirectories. I have made
makefiles for the individual subdirectories to make object files (each
subdir makes more than one obj file and puts them into a new 'obj'
dir). This part works fine for me.

Now, I am trying to write a top-level Makefile which should:
- go through each subdir and seek the obj files.
- make one shared obj (.so) file for each subdir (module).
- get a list of .so files (finally) by going to each subdir.
- link them all to get $(execname)

I do not know how to do the first 2 parts (there is way too much stuff
to learn in Make). This is what I have roughly come up with in the
top-level makefile:

all:
<tab> @for i in $(SUBDIRS); do \
(cd $$i; $(MAKE) $@); done

The above will only make the obj files in each subdirs. Ideally, I like
to see something that does this:

gcc -o <execname> <all the .so> <linking>
Any help on this will be very much appreciated!

Thanks,
Sri.

[j***@my-deja.com]

Post by v***@gmail.com
Hi,
I have small project which has several subdirectories. I have made
makefiles for the individual subdirectories to make object files (each
subdir makes more than one obj file and puts them into a new 'obj'
dir). This part works fine for me.
- go through each subdir and seek the obj files.
- make one shared obj (.so) file for each subdir (module).
- get a list of .so files (finally) by going to each subdir.
- link them all to get $(execname)
I do not know how to do the first 2 parts [...]

The best way to figure out something like this is to download any open
source project that has multiple build subdirectories, and see how
those
makefiles work.

Jonathan Schilling